(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
The efficiency of program operation in split-gate flash memory cells is, to a large extent, dependent on the speed of the programming and erasing operations. In traditional split-gate flash memory cells in which programming is accomplished by source side injection it is preferable to have very thin oxide spacers separating floating gates and control gates from select gates and bit lines. Thinner oxide spacers allow for greater programming speed. However, thinner oxide spacers could result in increased leakage current and lower yield and reliability. Floating gates of traditional split-gate flash memory cells have square cross-sections. The erasing operation is often accomplished by channel erasing, that is, by injection of charge from the floating gate to the underlying channel. A square floating gate cross-section does not provide very much of an increased electric field at the corners, which limits the speed of channel erasing attainable with traditional split-gate flash memory cells.
Source side programming in a traditional split-gate flash memory cell is shown in FIG. 1 and channel erasing in a traditional split-gate flash memory cell is shown in FIG.2. The traditional split-gate flash memory cell shown in FIGS. 1 and 2 is contained between conductive bit lines, 18, which connect to source regions, 24, and drain regions, 22, that are formed in a semiconductor region, 2. Bit line insulator regions, 20, insulate the bit lines, 18, from select gate lines, 14, which connect to select gates, 26 that are separated from the semiconductor region, 2, by a select gate insulator layer, 16. Charging towers, situated between bit lines connecting to drain regions and select gates, are comprised of a floating gate insulator layer, 4, separating floating gates, 6, from the semiconductor region, 2; control gates, 10, separated from the floating gates by an intergate gate insulator region, 8; top insulator regions, 12, isolating the control gates from the select gate lines, 14 and sidewall insulator spacers, 30 that insulate the floating gates and control gates from the bit lines, 18 and select gates, 26. Transfer gate towers, situated between bit lines connecting to source regions and select gates, are comprised of a floating gate insulator layer, 4, separating floating gates, 6, from the semiconductor region, 2; transfer gates, 28, separated from the floating gates by an intergate gate insulator region, 8; top insulator regions, 12, isolating the transfer gates from the select gate lines, 14 and sidewall insulator spacers, 30 that insulate the floating gates and floating gates from the bit lines, 18 and select gates, 26.
Referring to FIG. 1, there is depicted source side programming in a traditional split-gate flash memory cell. Channel electrons, 32, are accelerated by the lateral field E, 34, acting over the distance x, 36, which in traditional split-gate flash memory cells is also the thickness of the insulator spacer between the control gate and select gate and also the floating gate and select gate. The larger the field E the easier it is for electrons to attain sufficient energy so that they can readily overcome the barrier presented by the floating gate insulator layer and pass into the floating gate. Thus with larger fields, E, attained by an increased potential difference between the control gate and select gate, there is more efficient charge injection into the floating gate and greater programming speed. However, with the sidewall insulator spacer thickness being the same as the separation x, the field across the spacer is as large or larger than E, especially during channel erasing when the potential difference across the spacer is even larger than during programming. Low leakage requirements and other yield and reliability considerations place restrictions on the magnitude of the field across the sidewall insulator spacer and thus on the field E, thereby limiting the attainable programming speed.
Referring now to FIG. 2, there is depicted channel erasing in a traditional split-gate flash memory cell. In channel erasing an applied potential difference between the control gate, 10 and the semiconductor region, 2, sets up a field at the floating gate-floating gate insulator layer, 4, interface. Due to the action of this field electrons, 38, pass from the floating gate through the floating gate insulator layer and into the semiconductor region. The rate at which electrons are ejected from the floating gate, and therefore the erasing rate, is exponentially dependent on the interface field. In the vicinity of sharp corners of the floating gate at the interface there is an intensification of the interface field and a resulting even greater intensification of the erasing rate. In traditional split-gate flash memory cells using channel erasing the floating gate cross-section is square with corners, 40, which are not sharp enough for a significant intensification of the erasing rate.
U.S. Pat. No. 5,393,682 to Liu shows a method for making tapered polysilicon gates, the purpose being to reduce the sharpness of corners, thus improving step coverage and the quality of deposited layers around polysilicon edges. U.S. Pat. No. 5,723,371 to Seo et al. teaches a method for fabricating a thin film transistor having a taper-etched semiconductor film, where the sharpness of corners is reduced. Another process for tapered silicon films is shown in U.S. Pat. No. 5,728,259 to Suzawa et al. in a method of fabricating a semiconductor device in which a gate insulating layer has no plasma induced damage. In U.S. Pat. No. 6,228,695 B1 to Hsieh et al., a split-gate flash memory cell is shown with self-aligned source and self-aligned floating gate to control gate. The method replaces the conventional polysilicon oxidation process thereby yielding a sharper floating gate edge for improved programming and erasing. U.S. Pat. No. 6,259,131 B1 to Sung et al. shows a method of forming a polysilicon gale tip in split-gate flash memory cells for enhanced F-N tunneling.
It is a primary objective of the invention to provide a split-gate flash memory cell structure with increased programming and erasing speed with no increase in leakage current and no reduction in yield and reliability. It is another primary objective of the invention to provide a method of achieving a split-gate flash memory cell structure with increased programming and erasing speed with no increase in leakage current and no reduction in yield and reliability.
These objectives are achieved in split-gate flash memory cell structures according to the embodiments of the invention in which the floating gate has a trapezoidal cross-section. The structures of preferred embodiments of the invention allow for large electric fields to efficiently energize channel electrons in source side programming, while the sidewall insulator spacer thickness can be maintained large enough to preclude any leakage current, yield and reliability exposures. A trapezoidal cross-section allows for sharp corners facing the semiconductor region across the floating gate insulator layer. This leads to enhanced channel erasing speed.
A structure is disclosed for split-gate flash memory cells in which isolation regions separate parallel active regions within a semiconductor region. Trapezoidal floating gates, separated from the active regions by an insulator layer, are equally spaced over the active regions. Three tiered parallel strips run perpendicular to the active regions and pass over corresponding trapezoidal floating gates, the bottom and top tiers being insulator layers and the middle tier being a conductor layer. Insulator spacers are disposed over the sidewalls of the three-tiered parallel strips and of the trapezoidal floating gates. These parallel structures are designated floating gate towers. Source/drain regions are formed in the semiconductor region of every other opening between floating gate towers where they are contacted by source/drain contact lines. An insulator layer is disposed over the source/drain contact lines. The other openings between floating gate towers contain select gates, which are conductive columns that are separated from the semiconductor region by an insulator layer and rise over active regions. Parallel select gate contact lines are disposed over and run along the active regions contacting the select gates.